ABSTRACT
CMOS scaling will continue, doubling transistor integration
capacity every two years, providing billions of transistors to enable
future novel systems. 3D integration technology will open the doors
even further, changing the landscape and allowing integration of
diverse functionality to realize energy-efficient and affordable
complex systems that will continue to deliver higher performance.
This paper presents how to exploit this new technology for energy
efficient system design.
INTRODUCTION
Technology scaling treadmill will continue to follow Moore's
Law, providing integration capacity of billions, even trillions of
transistors, improving transistor performance, providing abundance
of interconnections to realize complex architectures, and reducing the
cost of transistor integration by half every generation.
First, the transistor performance improvement will be limited, and
you will not see historic doubling of frequency every two years.
The system designers will have to continue to deliver ever
increasing performance despite these challenges.
Monday, September 13, 2010
Friday, August 20, 2010
p7 Thermo-Mechanical Stress Characterization of Tungsten-Fill Through-Silicon-Via
Abstract
Thermo-mechanical stress of tungsten-filled (W-fill) through-silicon-via (TSV) is strongly depending on via shape, size and inter-via spacing, which places constraints on TSV design, including 2-D integrated circuit layout and 3-D structure profile.
1. Introduction
2. TSV Test Structure Design
3. TSV Patterning
4. Tungsten Film Stress
(page 2)
WF6 precursor CVD is chosen for deposition
of W as it is known to provide good conformal film
and high throughput.
5. Flexus Wafer Bow Characterization
A typical interconnection via fill requires
0.6μm W film deposition.\
6. Wright-Etch Characterization
7. Mechanical Stress Simulation
Stress in the substrate can develop as a result
of thermal expansion mismatch between the different
materials composing the TSV and the substrate
Figure 4 shows the model structure of a
30μm long, isolated 3-D structure of the TSV used in
the simulations
Substrate stress is also affected by
interactions between adjacent TSV in an array.
8. Summary & Discussion
The Through Silicon Via (TSV) stress
depends strongly on TSV shape, size, spacing, and 3-
D profile, which would place constraints on TSV
design.
Thermo-mechanical stress of tungsten-filled (W-fill) through-silicon-via (TSV) is strongly depending on via shape, size and inter-via spacing, which places constraints on TSV design, including 2-D integrated circuit layout and 3-D structure profile.
1. Introduction
2. TSV Test Structure Design
3. TSV Patterning
4. Tungsten Film Stress
(page 2)
WF6 precursor CVD is chosen for deposition
of W as it is known to provide good conformal film
and high throughput.
5. Flexus Wafer Bow Characterization
A typical interconnection via fill requires
0.6μm W film deposition.\
6. Wright-Etch Characterization
7. Mechanical Stress Simulation
Stress in the substrate can develop as a result
of thermal expansion mismatch between the different
materials composing the TSV and the substrate
Figure 4 shows the model structure of a
30μm long, isolated 3-D structure of the TSV used in
the simulations
Substrate stress is also affected by
interactions between adjacent TSV in an array.
8. Summary & Discussion
The Through Silicon Via (TSV) stress
depends strongly on TSV shape, size, spacing, and 3-
D profile, which would place constraints on TSV
design.
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